In semiconductor fabrication, a plurality of silicon dies are typically formed in parallel on a common substrate and further processed to encapsulate the dies in mold compound. After processing of the die-substrate assembly is completed, it is diced to separate or singulate the assembly into individual units.
One challenge in providing the encapsulation is that warpage may occur due to a mismatch in the Coefficient of Thermal Expansion (CTE) of the mold compound and the silicon die. This problem becomes aggravated when the encapsulation is carried out on an array of silicon dies mounted onto a common substrate such as in a wafer format, and even more so when the thickness of the silicon dies and the substrate decreases. Furthermore, when mounted onto a common substrate, the silicon dies may shift out of its designated location during molding. Additionally, another challenge faced by this form of assembly is optimising the number of dies that can be mounted onto the common substrate so as to maximise space savings.
Based on the foregoing discussion, the packages and/or package techniques are desirable to address one or more of the above disadvantages.